1. Field of the Invention
The present invention relates to phase-locked loop (PLL) circuits, and, more particularly, to adaptive loop bandwidth circuits for a PLL.
2. Description of the Related Art
A phase-locked loop (PLL) is a circuit that generates, or synthesizes, a periodic output signal that has a constant phase and frequency with respect to a periodic input signal. PLLs are widely used in many types of measurement, microprocessor, and communication applications. One type of phase-locked loop is the charge-pump PLL, which is described in Floyd M. Gardner, “Charge-Pump Phase-Lock Loops” IEEE Trans. Commun., vol. COM-28, pp. 1849-1858, November 1980, the teachings of which are incorporated herein by reference.
In a conventional charge-pump phase-locked loop, a phase detector (PD) compares the phase θIN of the input signal to the phase θOUT of a feedback signal derived from the PLL output. Based on the comparison, the PD generates an error signal: either an UP signal (when θIN leads θOUT) or a DOWN signal (when θOUT leads θIN), where the error signal indicates the magnitude of the difference between θIN and θOUT. A charge pump generates an amount of charge equivalent to the error signal from the PD, where the sign of that charge indicates the direction of UP or DOWN. Depending on whether the error signal was an UP signal or a DOWN signal, the charge is either added to or subtracted from the one or more capacitors in a loop filter. The loop filter may have a relatively simple design, comprising a capacitor CS in parallel with the series combination of a resistor R and a relatively large capacitor CL. As such, the loop filter operates as an integrator that accumulates the net charge from the charge pump. The resulting loop-filter voltage VLF is applied to a voltage-controlled oscillator (VCO). A voltage-controlled oscillator is a device that generates a periodic output signal, whose frequency is a function of the VCO input voltage. Input and feedback dividers may be placed in the input and feedback paths, respectively, if the frequency of the output signal is to be either a fraction or a multiple of the frequency of the input signal.
In digital data applications in which a locally generated clock is synchronized to input data, one type of PLL is implemented with a PD that observes discrete periods, or snapshots, of the phase error between the input data and the clock. The clock phase correction is based solely on the polarity, or direction, of the phase offset. This type of PD is sometimes referred to as a “bang-bang” PD. A bang-bang PD samples the phase error of the input data in the following way: one sample is taken near the optimal sampling point, termed the center of the eye, and a sample is also taken at or near the transition point where the data switches to a new logic level, termed the edge transition. PLLs with bang-bang PDs are only nearly “locked” to the input data and form non-linear systems that make analysis difficult.
If the sampled data is different from the value sampled during the prior edge transition (termed a prior “edge transition sample”), then the edge transition sample is made before the data changes to a new value. In this case, the system clock is leading, and the PD generates a DOWN signal to decrease the speed, or frequency, of the clock. Similarly, if the sampled data is different from the next edge transition sample, then the system clock is lagging, and the PD generates an UP signal to increase the frequency of the clock. However, bang-bang PDs may introduce excessive jitter in the resulting clock signal since the clock is shrunk or expanded at every edge transition.